1. Field of the Invention
The present invention pertains to the field of thin films for use in integrated circuits, and particularly ferroelectric thin films. More specifically, a specialized capping layer containing bismuth tantalate increases the dielectric breakdown voltage of bismuth-containing layered superlattice material thin films.
2. Statement of the Problem
A ferroelectric device, such as a capacitor, is useful as a nonvolatile memory when it possesses desired electronic characteristics, such as high residual polarization, good coercive field, high fatigue resistance, low imprint, low leakage current and high breakdown voltage. See, for example, U.S. Pat. No. 5,784,310 issued Jul. 21, 1998 to Cuchiaro et al. It is also possible to make a ferroelectric memory cell consisting of a field effect transistor as described in U.S. Pat. No. 5,780,886 issued Jul. 14, 1998 to Yamanobe et al. Layered superlattice material oxides have been studied for use in integrated circuits. U.S. Pat. No. 5,434,102, issued Jul. 18, 1995 to Watanabe et al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995 to Yoshimori et al., describe processes for integrating these materials into practical integrated circuits. Layered superlattice materials exhibit characteristics in ferroelectric memories that are orders of magnitude superiorto those of perovskite compounds, such as PZT and PLZT. As reported in U.S. Pat. No. 5,784,310 issued Jul. 21, 1998 to Cuchiaro et al., layered superlattice materials have relatively very good fatigue and imprint characteristics compared to other types of ferroelectric materials. However, layered superlattice materials typically required processing temperatures in excess of 700xc2x0 C. in order to achieve proper crystallization and the desired electronic propertied. This is an obstacle to the commercial utilization of layered superlattice materials in integrated circuits because other components of the circuits typically require that the fabrication processing temperatures not exceed 700xc2x0 C.
It is highly desirable that a ferroelectric memory be dense; that is, that there be a high number of memory cells in a given chip volume. To achieve maximum density, the individual elements of the memory should be as small as possible. This requires that the films of ferroelectric material be as thin as possible. However, generally, it has been found that the processing+parameters, such as annealing temperatures, necessary to produce integrated circuit quality electronic devices also cause films less than about 100 nm to crack or otherwise fail. U.S. Pat. No. 6,104,049, issued Aug. 15, 2000 to Solayappan et al. discloses a ferroelectric memory cell comprising a thin film of layered superlattice material having a thickness of 90 nm or less. The layered superlattice material is crystallized by RTP annealing at 675xc2x0 C. for 30 seconds followed by a post-anneal in oxygen or nitrogen for one hour at 700xc2x0 C. The Solayappan et al. patent disclosed a thin film of strontium bismuth tantalate (SBT) having a thickness of 90 nm with a 2Pr-value of 15 xcexcC/cm2 and a current density less than 10xe2x88x926 A/cm2 at an applied voltage of xc2x15 volts. After 1010 cycles, fatigue was less than 1.0% and imprint was about 20%.
However, the thin film process of Solayappan et al, while solving the temperature and thickness problems, still left other unresolved problems in trying to make a commercial, dense memory from layered superlattice materials. Specifically, the decrease in thin film thickness caused an undesirable increase in leakage current and an undesirable decrease in dielectric breakdown voltage. When a memory capacitor exhibits high leakage current, its power consumption increases and it is not able to store information over a long period because the charge polarization slowly dissipates as a result of undesired migration of charge carriers. It is currently held in the art that the current density measured in a memory capacitor should not exceed 10xe2x88x926 A/cm2 in the range of its operating voltages.
As the voltage is increased across the dielectric material of a memory capacitor, a point is ultimately reached beyond which the insulation is no longer capable of sustaining any further rise in voltage and breakdown ensues, causing a short to develop between the electrodes. In ferroelectric and nonferroelectric layered superlattice materials, as well as in other solid metal-oxide dielectrics, the initial breakdown results in the formation of a permanent conductive channel, which cannot support a reapplication of voltage.
A general model of dielectric breakdown assumes widespread injection of electrons from one electrode, impact-ionization by the injected electrons, accumulation of some of the generated positive charges in a few isolated locations, and self-egenerative conduction through one of those locations, leading to thermal runaway. Injection is by a tunneling mechanism with regions of higher current density provided by submicroscopic surface irregularities on the (intended to be plane) emitting electrode. As the thickness of dielectric thin films, including thin films of layered superlattice material, is reduced, breakdown voltage occurs at a lower voltage. It is believed that this relationship may be a function of the relative size of surface irregularities compared to the metal-oxide thin film thickness. The dielectric breakdown voltage of an integrated circuit memory capacitor should be about four times greater than its normal operating voltage.
U.S. patent application Ser. No. 09/229,883, filed Jan. 14, 1999, discloses a capping layer comprising a metal oxide selected from the group consisting of bismuth oxide, bismuth strontate, bismuth tantalate, bismuth niobate and bismuth niobium tantalate. The capping layers taught in the ""883 application have a thickness in a range of 3 nm to 30 nm and are disposed on the surface of a thin film of layered superlattice material between the thin film and an electrode. The ""883 application disclosed an exemplary capacitor in which a bismuth oxide, BiOx, capping layer having a thickness of about 10 nm was formed on the upper surface of a thin film of the ferroelectric strontium bismuth tantalate (SBT) layered superlattice material having a thickness of about 200 nm. The capacitor having a capping layer had a measured 2Pr-value of about 17 xcexcC/cm2 measured at 5 volts, which was an improvement in polarizability of about 30% compared to a capacitor without the bismuth oxide capping layer. It is noteworthy that the SBT thin film fabricated in accordance with the method of the ""883 application had a total thickness of 200 nm, which is thicker than currently required to achieve maximum integrated circuit density. Furthermore, the exemplary thin film of the ""883 application was annealed by RTP at 725xc2x0 C., and the capacitorwas given a post-anneal at 800xc2x0 C, which temperatures exceed the maximum feasible fabrication temperature of 700xc2x0 C. Finally, although the exemplary capacitor having a BiOx capping layer exhibited good polarizability, the ""883 application did not teach or otherwise disclose the leakage current or the dielectric breakdown voltage of capacitors having a capping layer.
To produce reliable and efficient nonvolatile ferroelectric memories in high-density memory integrated circuits, it would be highly desirable to have a ferroelectric thin film having a polarizability greater than 7 xcexcC/cm2, a thickness of about 100 nm or less, low leakage current and high dielectric breakdown voltage, that can be fabricated using a method compatible with other integrated circuit components.
The present invention advances the art and helps to overcome the aforementioned problems by increasing the dielectric breakdown voltage of a dielectric thin film of bismuth-containing layered superlattice material in integrated circuit devices. In particular, the invention provides improved thin film ferroelectric devices having good polarizability, low leakage current and high dielectric breakdown voltage. Integrated circuit devices in accordance with the invention, in particular, nonvolatile ferroelectric memory cells, contain a thin film of bismuth-containing layered superlattice material having a thickness of about 100 nm or less. A feature of the invention is that the films with low leakage current and high dielectric breakdown are produced by a method having process temperatures not exceeding 700xc2x0 C. These improvements, especially a relatively high dielectric breakdown voltage, are a result of a bismuth tantalate capping layer disposed on the surface of a thin film of bismuth-containing layered superlattice material between an electrode and the thin film.
A device in accordance with the invention includes a substrate supporting a thin film of bismuth-containing layered superlattice materials. The thin film of layered superlattice material is xe2x80x9ccappedxe2x80x9d on one or both of the top and bottom surfaces by a capping layer comprising bismuth tantalate, that is, bismuth tantalum oxide. Preferably, the capping layer contains an excess of bismuth relative to the stoichiometrically balanced amount. Preferably, the excess amount of bismuth is in a range of from 5% to 15%, and most preferably is 7.5%. An electrode is typically above or below the capping layer, and preferably resides in direct contact with both the electrode and the thin film of bismuth-containing layered superlattice material. Preferably, the capping layer caps the layered superlattice material beneath the top electrode, but if there are two electrodes, such as in a ferroelectric capacitor, the capping layer may cap both the top and bottom of the thin film of layered superlattice material.
A capping layer in accordance with the invention is useful for capping a thin film of either a ferroelectric or a nonferroelectric bismuth-containing layered superlattice material. Preferred ferroelectric bismuth-containing layered superlattice materials are selected from the group consisting of strontium bismuth tantalate, strontium bismuth niobate, and strontium bismuth niobium tantalate.
The capping layer is preferably at least about 3 nm thick, and preferably ranges from 3 nm to 30 nm in thickness, with the most preferred thicknesses ranging from 5 nm to 20 nm to provide adequate defect compensation while being thin enough to avoid significant problems with parasitic capacitance.
The use of a capping layer comprising bismuth tantalate is critical for achieving the desired increase in dielectric breakdown voltage. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.